The present invention relates to a semiconductor memory, and more particularly to a technique for repairing a semiconductor memory in such a manner that defective memory cells are replaced by spare memory cells.
In recent years, the level of integration of a semiconductor memory has been increased at high speed, and a semiconductor memory having a storage capacity of 1 mega bits has been mass-produced. However, as the level of integration of a semiconductor memory is made larger, each element is decreased in size, and the semiconductor chip is increased in area. Thus, there arises a problem that the manufacturing yields of the memory become correspondingly reduced. In order to solve the problem, the so-called redundancy technique is used, in which defective memory cells are replaced by spare memory cells already provided on a chip. As discussed on pages 479 to 487 of the IEEE, Journal of Solid-State Circuits, Vol. SC-16, No. 5, Oct., 1981, the above technique is very effective for improving the manufacturing yields of a semiconductor memory.
In addition to the above technique, a redundancy method is proposed in JP-A-60-130,139, in which method a regular line in one of a plurality of memory mats can be replaced by a spare line in another memory mat. In this method, however, there arises the following problem That is, in a case where a semiconductor memory is divided into a large number of memory mats, a complicated control operation is required to specify one of the memory mats. This is because a predetermined or another memory mat has to be selected in accordance with, whether or not an address to be accessed is defective. Specifically, in a case where a memory mat other than the predetermined memory mat is selected in a DRAM, it is required to operate a sense amplifier other than a predetermined sense amplifier Thus, the access time associated with operation of the memory is increased.